Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a storage capacitor that stores the data in the cell and an access transistor that controls access to the data. The charge stored across the capacitor is representative of a data bit and is usually either a high voltage, logic 1, or a low voltage, logic 0.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each such memory cell is associated with two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are generally associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line or row decoder and to a digit line or column decoder. The row decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the digit line address. For a read operation, the data corresponding to the selected memory cell is sensed, and the data and its complement are each latched to one digit line of the digit line pair. The column decoder further selects the digit line containing the data corresponding to the addressed memory cell for output.
The ability to sense the data stored in the storage capacitor is a critical operation of the memory device. This ability is a function of the sensitivity of the sense amplifiers to the potential differential, or cell margin, across the digit line pair. Increasing the signal-to-noise ratio thus improves the reliability of the sensing operation. Increasing the signal-to-noise ratio generally results from the increase in beta ratio, which is the ratio of the capacitance of the memory cell to the capacitance of the digit line. Increasing the beta ratio is often accomplished by isolating one half of the digit line pair from the sense amplifier.
In addition to improving reliability of the sensing operation, increases in beta ratio also permit lower power consumption in a memory device. By increasing the beta ratio, larger charge leakage is tolerable in the storage capacitor without adversely affecting the sensing operation. This permits lower refresh rates and, thus, lower power consumption.
Devices having insufficient beta ratio or excessive charge leakage are generally unsuited for their intended uses. While many causes of insufficient beta ratio and excessive charge leakage may be curable through the use of redundant devices, as is well known in the art, some causes may be global such that the redundant device also exhibits insufficient beta ratio or excessive charge leakage. Accordingly, there is a need in the art for devices capable of modifying the ratio of storage capacitance to digit line capacitance, and methods of their use.